Tunable quadrature phase shifter

ABSTRACT

The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means ( 10 ) for splitting the input signal into two essentially orthogonal first and second signals (i 1 , i 2 ), adding means ( 6 ) for adding said first and second signals (i 1 , i 2 ), subtracting means ( 7 ) for subtracting said first and second signals (i 1 , i 2 ), a first output (OUT+) for outputting a first output signal (vo 1 ) based on the output signal from said adding means ( 6 ), and a second output (OUT−) for outputting a second output signal (vo 2 ) based on the output signal from said subtracting means ( 7 ), wherein that said splitting means ( 10 ) is provided as an all-pass.

[0001] The present invention relates to a tunable quadrature phaseshifter comprising an input means for inputting an input signal,splitting means for splitting the input signal into two essentiallyorthogonal first and second signals, adding means for adding said firstand second signals, subtracting means for subtracting said first andsecond signals, a first output for outputting a first output signalbased on the output signal from said adding means, and a second outputfor outputting a second output signal based on the output signal fromsaid subtracting means.

[0002] Such a phase shifter which provides two output signals inquadrature are used in e.g. mobile communication systems and other radiotransmitter and receiver systems where an accurate 90 degrees phaseshift is necessary to obtain a sufficient image rejection in thetransmitter and to have a correct 90 degrees phase difference betweenthe I (In-phase) and Q (Quadrature-phase) base band phase vector signalsin the receiver. In particular, a possible application is the I/Qgeneration for RC/LC oscillators with large tuning range (“Sonet”/“SDH”applications). Further, such a phase shifter is used in polyphasefilters, QUAMs, Low IF/Zero IF receivers as well as Data and ClockRecovery (DCR) and Phase-Looked-Loop (PLL) circuits.

[0003] Among the first known techniques for quadrature signal generationis the RC-CR technique shown in FIG. 1. Here, an input signal vin isshifted by −π/4 to form a first output signal vo1 and by +π/4 to form asecond output signal vo2. The phase difference between the outputsignals vo1 and vo2 is always π/2, but the amplitudes of the outputsignals vo1 and vo2 are equal at one frequency fo=1/(2πRC) only.

[0004] After shifting, limiting stages (not shown in FIG. 1) can beused, but amplitude limiting becomes difficult in the GHz range unlessseveral stages are connected in cascade. This operation is possible incase only zero crossings of the signal are relevant. Nevertheless, thereis always a mismatch in gain and amplitude between both the outputsignals vo1 and vo2 in the two parallel paths. Moreover, due tononlinear effects, slew-rate (dvin/dt) like AM to PM conversion occurs.When the RC time constant varies with process and temperature, thecutoff frequency at which the amplitudes of both the output signals vo1and vo2 are equal varies, too. Besides, the mismatch between passivecomponents results also in a phase mismatch.

[0005] Another conventional method for quadrature generation is theHavens technique according to FIG. 2. The input signal is splitted intotwo branches by using a quadrature circuit 2 which has approximatelyquadrature outputs. The precision of this circuit is not mandatory.These two signals are:

ν1(t)=Acos(ωt)

ν2(t)=Acos(ωt+θ)  (1).

[0006] After each of these two signals vo1 and vo2 is limited inamplitude by a limiter 4 and 5, respectively, these two signals areadded by an adder 6 and also subtracted by a subtracter 7. Each of thesignals from the outputs of the adder 6 and subtracter 7 are againlimited in amplitude by limiters 8 and 9, respectively, to form theoutput signals vo1 and vo2. The interesting part comes from the factthat a phase imbalance from π/2 gives afterwards an amplitude mismatchbetween the two signals v1 and v2 cancelled away by the limiting action.This operation is explained below: $\begin{matrix}{{{{v1} + {v2}} = {2A\quad {\cos \left( \frac{\theta}{2} \right)}{\cos \left( {{\omega \quad t} + \frac{\theta}{2}} \right)}}}{{{v1} - {v2}} = {2A\quad {\sin \left( \frac{\theta}{2} \right)}{{\sin \left( {{\omega \quad t} + \frac{\theta}{2}} \right)}.}}}} & (2)\end{matrix}$

[0007] The amplitudes A of the sum and difference signals are equal ifthe phase shifter has two outputs in quadrature (θ=π/2). Assuming thatin the second signal v2 there is an amplitude mismatch of magnitude ε,the equation for the second signal v2 reads as follows:

ν2=(A+ε)cos(ωt+θ)  (3).

[0008] The effect of such error is that v1+v2 rotates counterclockwiseby Φ1 and v1−v2 clockwise by Φ2. In FIG. 3 the phasor diagram of thesignals is shown. The two situations depicted correspond to thesituation when no amplitude errors are present (FIG. 3a) and thesituation when amplitude errors are present (FIG. 3b). From FIG. 3 onecan find the phase errors Φ1 and Φ2 and the local phase error Φ1+Φ2under the assumption that the a error ε is small when compared with theamplitude A, i.e. ε<<A.

[0009] The equations for the phase errors Φ1 and Φ2 are $\begin{matrix}{{{\tan ({\Phi 1})} = \frac{ɛ\quad {\sin \left( \frac{\theta}{2} \right)}}{{2A\quad {\cos \left( \frac{\theta}{2} \right)}} + {{ɛcos}\left( \frac{\theta}{2} \right)}}}{{\tan ({\Phi 2})} = {\frac{ɛ\quad {\cos \left( \frac{\theta}{2} \right)}}{{2A\quad {\sin \left( \frac{\theta}{2} \right)}} + {{ɛsin}\left( \frac{\theta}{2} \right)}}.}}} & (4)\end{matrix}$

[0010] When ε<<A the result is: $\begin{matrix}{{{\Phi 1} + {\Phi 2}} \cong {\frac{ɛ}{A\quad {\sin (\theta)}}.}} & (5)\end{matrix}$

[0011] The amplitude mismatch ε leads to a phase mismatch. 1% amplitudemismatch generates 0.6° in phase. Although this method is better interms of robustness to errors, the disadvantage consists in the use ofthe four limiters 4, 5, 8 and 9 which convert amplitude modulation intophase modulation. Another critical disadvantage is that even someamplitude errors are tolerated, the input quadrature generator producesfor different frequencies unequal amplitudes. Therefore, when the abovedescribed quadrature generation circuit is coupled to oscillators forI/Q processing by tuning the oscillator within an octave for example,the amplitude of the two paths drastically varies.

[0012]FIG. 2 shows the closest prior art from which the inventionproceeds.

[0013] EP 0 707 379 A1 discloses a tunable quadrature phase shifterincluding two branches each constituted by cascade connection of afilter, an amplifier and a summing circuit, and two cross-connectionsconstituted by amplifiers interconnecting the filter of one branch tothe summing circuit of the opposite branch. An accurate 90° phase shiftbetween the two output signals is obtained by controlling the tailcurrents of the four amplifiers.

[0014] WO 92/11704 A1 describes a quadrature signal generator includinga phase-locked loop configuration which comprises a voltage controlphase-shift network, limiters, an exclusive-OR phase detector, a lowphase filter, a differential voltage to current converter and a loopfilter. The voltage controlled phase-shift network generates a phaseshift for the differential quadrature signals. The exclusive-OR phasedetector determines the phase error between the differential quadraturesignals. The phase error is related to a voltage control signal which iscoupled back to the voltage controlled phased-shift network to maintaina precise 90° phase relationship between the differential quadraturesignals.

[0015] Due to the control mechanism, both the devices according to EP 0707 379 A1 and WO 92/11704 A1 require a complex and expensiveconstruction.

[0016] Accordingly, it is an object of the present invention to providea simple construction which avoids the amplitude mismatch and can beused for oscillators with more than one octave frequency tuning.

[0017] In order to achieve the above and other objects, according to thepresent invention, there is provided a tunable quadrature phase shiftercomprising an input means for inputting an input signal, splitting meansfor splitting the input signal into two essentially orthogonal first andsecond signals, adding means for adding said first and second signals,subtracting means for subtracting said first and second signals, a firstoutput for outputting a first output signal based on the output signalfrom said adding means, and a second output for outputting a secondoutput signal based on the output signal from said subtracting means,characterized in that said splitting means is provided as an all-pass.

[0018] Since an all-pass produces two quadrature signals with equalamplitudes and the gm/C time constant of an all-pass tracks theoscillation frequency (using the same tuning mechanism) of the inputsignal outputted by the oscillator, the amplitude mismatch is wellreduced. This further allows to avoid limiters at the input and also atthe output. So, the present invention uses gm/C tuning schemes withinherent I/Q matching.

[0019] Preferably, a first output buffer means for buffering said firstoutput signal and a second output buffer means for buffering said secondoutput signal are provided.

[0020] A further preferred embodiment of the present invention comprisesa first transimpedance converter having its input connected to saidinput means. A modification of this embodiment still comprises a secondtransimpedance converter having its output connected to said firstoutput and a third transimpedance converter having its output connectedto said second output. The provision of transimpedance converters isrecommended in case the input and output signals are provided as voltagesignals. Usually, the transimpedance converters are transimpedanceamplifiers.

[0021] In accordance with a still further preferred embodiment of thepresent invention, the first and second output buffer means are providedas said first and second transimpedance converters, respectively, sincethe transimpedance converters have buffering functions, too.

[0022] A further preferred embodiment of the present invention ischaracterized by at least a first transistor with its collectorconnected to its base and its emitter coupled to a predeterminedpotential, a second transistor with its base connected to the base ofsaid first transistor and its emitter coupled to said predeterminedfixed potential, and a capacitor coupled between the junction of thebases of said first and second transistor and said predeterminedpotential.

[0023] In case the tunable quadrature phase shifter is provided as adifferential phase shifter, further preferred embodiment ischaracterized by at least a first transistor with its collectorconnected to its base and its emitter coupled to a predeterminedpotential, a second transistor with its base connected to the base ofsaid first transistor and its emitter coupled to said predeterminedpotential, a third transistor with its collector connected to its baseand its emitter coupled to a predetermined potential, a fourthtransistor with its base connected to the base of said third transistorand its collector coupled to said predetermined potential, and acapacitor coupled between a first junction of the bases of said firstand second transistors and a second junction of the bases of said thirdand fourth transistors.

[0024] In both recently above mentioned embodiments, the transistors canbe npn transistors and/or the predetermined potential is zero (ground).

[0025] The above and other objects and features of the present inventionwill become clear from the following description taken in conjunctionwith the preferred embodiment with reference to the accompanyingdrawings in which:

[0026]FIG. 1 shows a first conventional quadrature phase shifter using asimple RC-CR technique;

[0027]FIG. 2 shows a second conventional quadrature phase shifter usingthe Havens technique;

[0028]FIGS. 3a and b show phasor diagrams for the Havens technique usedin the second conventional phase shifter;

[0029]FIG. 4 shows a quadrature phase shifter in accordance with apreferred embodiment of the present invention;

[0030]FIG. 5a circuit diagram of an all-pass network comprising pnp andnpn transistors;

[0031]FIG. 6a circuit diagram of an all-pass network for quadraturegeneration at transistor level view;

[0032]FIG. 7 an embodiment of a bang-bang phase detector including aquadrature phase shifter (a) and wave forms of the input and outputsignals of the quadrature phase shifter (b); and

[0033]FIG. 8 an embodiment of a data and clock recovery unit includingthe bang-bang phase detector of FIG. 7.

[0034] In FIG. 4 is shown a preferred embodiment of the presentinvention.

[0035] The architecture shown in FIG. 4 mainly differs from theconventional architecture of FIG. 2 in that instead of the quadraturecircuit 2 an all-pass circuit 10 is provided which produces twoquadrature signals with equal amplitudes.

[0036] In the preferred embodiment of FIG. 4, the input signal vininputted at the input terminal IN is supplied to an input transimpedanceamplifier 12. In the input transimpedance amplifier 12, the input signalvin is buffered and a voltage to current conversion takes place since inthe preferred embodiment shown in FIG. 4 the input signal vin is avoltage signal. However, an input transimpedance amplifier 12 is notnecessary in case the input signal vin is not a voltage signal, but acurrent signal.

[0037] The current signal iin outputted from the input transimpedanceamplifier 12 is fed to the all-pass circuit 10 having two outputs andproducing two quadrature signals with equal amplitudes. Since the gm/Ctime constant of the all-pass circuit 10 tracks the oscillationfrequency (using the same tuning mechanism) of the input signal vinwhich is generated by an oscillator (not shown in FIG. 4), the amplitudemismatch is well reduced, and the signals i1 and i2 outputted from theall-pass circuit 10 are always in quadrature.

[0038] The quadrature signals i1 and i2 outputted by the all-passcircuit 10 are added by an adder 6 and further subtracted by asubstractor 7 in the same manner as in the conventional architecture ofFIG. 2.

[0039] The sum signal outputted from the adder 6 and the differencesignal outputted from the subtractor 7 are applied to the input of firstand second output transimpedance amplifiers 14 and 15 which buffer thesesignals and again convert them to voltage signals vo1 and vo2. Thesevoltage signals vo1 and vo2 are the output signals outputted at theoutputs OUT+ and OUT−. However, such output transimpedance amplifiers 14and 15 are not necessary in case the output signal should remain acurrent signal.

[0040] Given the fact that the outputs of the all-pass circuit 10 arecurrents, in a differential implementation the two signals i1+i2 andi1−i2 can be easily generated. This is realized at the inputs of theoutput transimpedance amplifiers 14 and 15.

[0041] The all-pass transfer function is considered as follows:$\begin{matrix}{{{H(s)} = \frac{{{sC}/g_{m}} - 1}{{{sC}/g_{m}} + 1}};\quad {s = {j\omega}}} & (6)\end{matrix}$

[0042] where C/g_(m) is the time constant of the all-pass circuit 10which can be tuned by tuning the transconductance g_(m). The phase-shiftof the all-pass circuit 10 depends on the frequency as follows:$\begin{matrix}{{\varphi (\omega)} = {\pi - {2{{\arctan \left( \frac{\omega \quad C}{g_{m}} \right)}.}}}} & (7)\end{matrix}$

[0043] The phase-shift of the network is π/2 when ω=g_(m)/C. The timeconstant can be tuned such that this condition is always fulfilled. Now,the two signals i1+i2 and i1−i2 can be generated as follows:$\begin{matrix}{{{{i1} + {i2}} = {{i_{i} + {i_{i}\left( \frac{{{sC}/g_{m}} - 1}{{{sC}/g_{m}} + 1} \right)}} = {{2i_{i}} - \frac{2i_{i}}{{{sC}/g_{m}} + 1}}}}{{{i1} - {i2}} = {{i_{i} - {i_{i}\left( \frac{{{sC}/g_{m}} - 1}{{{sC}/g_{m}} + 1} \right)}} = \frac{2i_{i}}{{{sC}/g_{m}} + 1}}}} & (8)\end{matrix}$

[0044] In order to simplify the understanding of the circuit, referenceis made to FIG. 5. Here, the input current I_(i) is mirrored at theinput of the phase shifter and at its output.

[0045] Assuming that C dominates over the parasitics seen at the samenode and the current gain factor between the two npn transistors T₁ andT₂, of FIG. 5, it is easy to show that the transfer function of thecircuit is: $\begin{matrix}{\frac{I_{0}}{I_{i}} = {\frac{{{sC}/g_{m}} - 1}{{{sC}/g_{m}} + 1}.}} & (9)\end{matrix}$

[0046] If the total circuit is biased with a DC current I_(BIAS), thetime constant C/g_(m) of the network is tuned by changing I_(BIAS) so asto change the transconductance g_(m).

[0047] In a differential approach, pnp transistors are, however, notnecessary, and therefore the clue is to generate the two signals i1+i2and i1−i2 without the need for pnp transistors. Namely, it has beenfound that pnp transistors have bad frequency characteristics. Apreferred embodiment of an circuit for the differential implementationof the quadrature generation is shown in FIG. 6.

[0048] The input voltage at IN+ and IN− is converted into current byusing the emitter degenerated differential pair. Matching betweencurrents is improved and also the linearity when compared to thesituation without degeneration. At the summation node A of thetransimpedence amplifier, the netto current flowing is: $\begin{matrix}{i_{A} = {\frac{2i_{i}}{{{sC}/g_{m}} + 1} - {2i_{i}}}} & (10)\end{matrix}$

[0049] which looks like the negative output of the differential currenti1+i2 from equation (8). At the subtraction node B, the netto currentflowing is: $\begin{matrix}{i_{B} = {\frac{2i_{i}}{{{sC}/g_{m}} + 1}.}} & (11)\end{matrix}$

[0050] This reminds of i1−i2 from equation (8). The assumption in theequations (10) and (11) is that DC currents are not flowing at theoutput and only signal currents are passed to the output.

[0051] The implementation of the quadrature phase shifter in a bang-bangphase detector 20 is shown in FIG. 7a wherein the quadrature phaseshifter is depicted as block 22. The quadrature phase shifter 22 outputstwo signals CKI and CKQ corresponding to the output signals vo1 and vo2as shown in FIGS. 1, 2 and 4. As further shown in FIG. 7a, the input ofthe quadrature phase shifter 22 is connected to an output of a voltagecontrolled oscillator (VCO) 24. A tuning signal vtune is input into theVCO 24. The output signal of the VCO 24 is the input signal of thequadrature phase shifter 22 and corresponds to vin of FIGS. 1, 2 and 4.

[0052] The bang-bang detector 20 further comprises several D flip-flopsDFF1 to DFF4 and DFF1′ to DFF4′. The two output signals CKI and CKQ ofthe quadrature phase shifter 22 are used to clock the D flip-flops.Further, the bang-bang detector 20 comprises a phase detector lodging 26which is controlled by the D flip-flops.

[0053] The wave forms of the input and output signals of the quadraturephase shifter 22 are shown in FIG. 7b.

[0054] The bang-bang detector of FIG. 7a is an interleaved version of anAlexander bang-bang phase detector based on quadraturevoltage-controlled oscillation, wherein the VCO 24 is a LC-VCO withoutquadrature outputs and the quadrature generation is done outside the VCO24 by the quadrature phase shifter 22. Since the quadrature generationis done outside the VCO 24, the phase noise of the oscillator is notimpaired.

[0055]FIG. 8 shows a data and clock recovery unit including thebang-bang detector of FIG. 7.

[0056] The advent of fiber optic communications has brought fullyintegrated optical receivers in which low-power becomes a must in orderto cope with higher integration densities and the limited thermalcapabilities of existing packages. At the receiver side, data and clockrecovery units (DCR), PLL based, are needed to recover the clockinformation and to retime the incoming data. The data and clock recoveryunit of FIG. 8 is based on a Master-Slave approach. This principlerelies on matched oscillators and two control loops for frequency andphase acquisition respectively. At the transmitter part, a clockconversion circuit has to provide a pure clock to control thetransitions of the data transmitted on fiber.

[0057] In clock-conversion circuits, PLL synthesizers are employed togenerate a pure clock by cleaning-up the phase noise of the VCO. LCoscillators have inherently better phase noise performance than RCoscillators alleviating the requirements on the PLL loop bandwidth. Infact, an LC-VCO allows the use of a narrow-band loop with superiorjitter transfer and low jitter generation. Another advantage of an LCoscillator consists in the frequency stability and the robustnesstowards temperature and process variations. The price usually paid isless tuning-range since integrated varicaps have limited capacitancevariation with voltage. In such designs, a fundamental trade-off is thetunability versus phase-noise. As phase-noise is inversely proportionalwith the square of the quality factor of the tank circuit and thederivative of the phase of the LC tank is directly proportional with Q,it is obvious that one cannot get very good phase-noise performancealong with large tuning ranges. By integrating the VCO with the completeLC tank the interference from outside world can be better controlled,and the pin-count can be better reduced. The aim of this paper is toshow that one can achieve 1 GHz tuning range with an LC oscillator withlow phase-noise by taking advantage of temperature and processvariations compensation techniques. The design has been realized in a 30GHz fT BiCMOS process making use only of MOS transistors in the VCO coreand fast bipolar buffers for I/Q interfacing.

1. Tunable quadrature phase shifter comprising an input means (IN) forinputting an input signal (vin; iin), splitting means (10) for splittingthe input signal into two essentially orthogonal first and secondsignals (i1, i2), adding means (6) for adding said first and secondsignals (i1, i2), subtracting means (7) for subtracting said first andsecond signals (i1, i2), a first output (OUT+) for outputting a firstoutput signal (vo1) based on the output signal from said adding means(6), and a second output (OUT−) for outputting a second output signal(vo2) based on the output signal from said subtracting means (7),characterized in that said splitting means (10) is provided as anall-pass.
 2. Phase shifter in accordance with claim 1, characterized bya first output buffer means (14) for buffering said first output signal(vo1), and a second output buffer means (15) for buffering said secondoutput signal (vo2).
 3. Phase shifter in accordance with claims 1 or 2,characterized by a first transimpedance converter (12) having its inputconnected to said input means (IN).
 4. Phase shifter in accordance withat least any one of claims 1 to 3, characterized by a secondtransimpedance converter (14) having its output connected to said firstoutput (OUT+), and a third transimpedance converter (15) having itsoutput connected to said second output (OUT−).
 5. Phase shifter inaccordance with claims 3 and/or 4, characterized in that thetransimpedance converter (12; 14; 15) is a transimpedance amplifier. 6.Phase shifter in accordance with claims 2 and 4, characterized in thatsaid first and second output buffer means are said second and thirdtransimpedance converters (14, 15), respectively.
 7. Phase shifter inaccordance with at least any one of claims 1 to 6, characterized by atleast a first transistor (T₁) with its collector connected to its baseand its emitter coupled to a predetermined potential, second transistor(T₂) with its base connected to the base of said first transistor andits emitter coupled to said predetermined fixed potential, and acapacitor (C) coupled between the junction of the bases of said firstand second transistor (T₁, T₂) and said predetermined potential. 8.Phase shifter in accordance with at least any one of claims 1 to 6,provided as a differential phase shifter comprising a first input (IN+)for inputting an input signal, and a second input (IN−) for inputting aninverse input signal, characterized by at least a first transistor withits collector connected to its base and its emitter coupled to apredetermined potential, a second transistor with its base connected tothe base of said first transistor and its emitter coupled to saidpredetermined potential, a third transistor with its collector connectedto its base and its emitter coupled to a predetermined potential, afourth transistor with its base connected to the base of said thirdtransistor and its collector coupled to said predetermined potential,and a capacitor (2C) coupled between a first junction of the bases ofsaid first and second transistors and a second junction of the bases ofsaid third and fourth transistors.
 9. Phase shifter in accordance withclaims 7 or 8, characterized in that said transistors are npntransistors.
 10. Phase shifter in accordance with at least any one ofclaims 7 to 9, characterized in that said predetermined potential iszero (ground).
 11. Data and clock recovery unit comprising a phasedetector (20) which includes a phase shifter in accordance with at leastany one of the preceding claims.